Code Optimizers and Register Organizations for Vector Architectures
Description:... In the second half of this dissertation, I investigate the cost and performance of different organizations for a vector register file in the Cray Y-MP vecto processor, and investigation that emphasizes the interaction between processor design and compiler algorithms. After showing that instruction scheduling has a major impact on how effectively more vector registers can be used, I present data from simulation experiments indicating that 16 vector registers and the scheduling algorithm can improve peformance significantly over that of 8 vector registers and the scheduling algorithm used in the Cray vectorizing compiler. I also investigate the usage of an alternative register organization, called a partitioned vector register file, which is less costly to implement than a traditional one but places some restrictions on accessing vector registers and present data showing that, when using my algorithm, the performance of a partitioned vector register file is comparable to that of a traditional one.
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