Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

• Author(s): Brandon Noia, Krishnendu Chakrabarty,
• Publisher: Springer Science & Business Media
• Pages: 245
• ISBN_10: 3319023780
  ISBN_13: 9783319023786
  
• Language: en
• Categories: Technology & Engineering / Electronics / Circuits / General , Computers / Computer Architecture , Technology & Engineering / Electronics / Semiconductors , Technology & Engineering / Electrical , Technology & Engineering / Superconductors & Superconductivity ,

Description:... This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.